From the Silicofeller blog.

Research, engineering, and industry insights from our team.

Quantum Computing and National Security: Why Governments Are Spending Billions in 2026

Jul 18, 2026
Industry & Milestones

The US, EU, China, and India have collectively committed over $50 billion to quantum technology programmes. Harvest-now-decrypt-later attacks, post-quantum cryptography deadlines, and quantum sensing are driving a geopolitical race. Here's the full picture.

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Quantum Computing and National Security: Why Governments Are Spending Billions in 2026

Google Willow: The Quantum Chip That Solved a 10-Septillion-Year Problem in 5 Minutes

Jul 14, 2026
Industry & Milestones

Google's Willow chip achieved a landmark milestone — completing a benchmark computation in under 5 minutes that would take today's fastest supercomputers 10 septillion years. Here's what it means for the future of quantum computing.

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Google Willow: The Quantum Chip That Solved a 10-Septillion-Year Problem in 5 Minutes

Microsoft's Topological Qubits: A New Era of Fault-Tolerant Quantum Hardware

Jul 10, 2026
Quantum Computing

Microsoft has unveiled its first topological qubit device based on Majorana zero modes, claiming error rates orders of magnitude lower than conventional transmon qubits. We break down the physics and what it means for scalable quantum computing.

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Microsoft's Topological Qubits: A New Era of Fault-Tolerant Quantum Hardware

Quantum Error Correction Hits Below Threshold: The Road to Practical Fault Tolerance

Jul 5, 2026
Theory & Research

Multiple labs have now demonstrated logical error rates below the fault-tolerance threshold. We explain the surface code, recent experimental results from Google, IBM, and IQM, and what 'below threshold' actually means for the path to a million-qubit machine.

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Quantum Error Correction Hits Below Threshold: The Road to Practical Fault Tolerance

How AI Is Automating Quantum Chip Design — From Prompt to GDS in Minutes

Jul 1, 2026
Developer Tools & Tech

AI-driven design tools are transforming how quantum chips are built. We explore how large language models, physics-grounded layout engines, and automated DRC are collapsing the design cycle from months to hours.

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How AI Is Automating Quantum Chip Design — From Prompt to GDS in Minutes

IBM Heron & the 100,000-Qubit Roadmap: What IBM Quantum's Latest Chips Tell Us

Jun 28, 2026
Industry & Milestones

IBM's Heron processor introduces a new coupler architecture that cuts crosstalk by 100× compared to Eagle. We analyse the architectural choices, benchmark results, and IBM's ambitious path to a 100,000-qubit system by 2033.

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IBM Heron & the 100,000-Qubit Roadmap: What IBM Quantum's Latest Chips Tell Us

Superconducting vs Trapped Ion vs Photonic: Which Qubit Technology Wins in 2026?

Jun 25, 2026
Quantum Computing

With Google, IBM, IonQ, Quantinuum, and PsiQuantum all racing toward fault-tolerant quantum computing using different physical platforms, we do a head-to-head comparison of the leading qubit technologies on coherence, gate fidelity, connectivity, and scalability.

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Superconducting vs Trapped Ion vs Photonic: Which Qubit Technology Wins in 2026?

HFSS: High Frequency Structure Simulator — A Complete Guide for Quantum Engineers

Jun 23, 2026
Hardware Engineering

HFSS is a full-wave 3D electromagnetic field solver developed by Ansys. It uses the Finite Element Method (FEM) to compute field distributions in arbitrary 3D geometries—making it the industry-standard tool for superconducting quantum circuit design.

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HFSS: High Frequency Structure Simulator — A Complete Guide for Quantum Engineers

HFSS Simulation Output Parameters: 52-Parameter Reference for Quantum Computing

Jun 23, 2026
Hardware Engineering

A comprehensive reference cataloguing 52 output parameters extracted from HFSS simulations for superconducting quantum circuit design, organised into 7 categories with design rules sourced from IEEE/APS research papers spanning 2004–2026.

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HFSS Simulation Output Parameters: 52-Parameter Reference for Quantum Computing

Q3D Extractor Output Parameters: RLGC Matrices & Parasitic Extraction for Superconducting Qubits

Jun 23, 2026
Hardware Engineering

Q3D Extractor is the industry-standard tool for parasitic extraction. This reference catalogues 47+ output parameters across 11 categories, with design rules for superconducting circuits.

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Q3D Extractor Output Parameters: RLGC Matrices & Parasitic Extraction for Superconducting Qubits

EPR Analysis Output Parameters: A Complete Reference

Jun 23, 2026
Hardware Engineering

The Energy Participation Ratio (EPR) method extracts quantum Hamiltonian parameters from classical EM simulations. This guide details all 50 parameters across 5 categories.

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EPR Analysis Output Parameters: A Complete Reference